1. Field of the Invention
The present invention relates to an emulation system for performing emulation operations on a core-type central processing unit (CPU) provided in an integrated circuit (IC). In the CPU construction of a core type, the CPU is integrated on the silicon substrate together with peripheral circuits. Such a CPU construction will be referred to as a CPU core, hereinafter. A core CPU is in contrast to a standalone CPU chip, which does not have other devices provided on the IC substrate in addition to the CPU core. The present invention also relates to an application-specific integrated circuit (abbreviated ASIC, hereinafter) provided with a CPU core such as mentioned above.
2. Related Art
With reference to FIG. 1, a general construction of a system comprising a CPU core such as described above will be described. An IC 3 including the CPU core 1 has a system bus 2 therein. The terminals associated with the CPU core 1 are connected to the system bus 2. Other circuit devices are also provided in the IC 3 and are connected to the system bus 2. Thus, the other circuit devices are connected to the CPU core 1 via the system bus 2. The IC 3 performs a predetermined operation where data is transferred via the system bus 2 between the CPU core 1 and the other circuit devices connected to the system bus 2. In order to perform data transfer between the CPU core 1 and an external device, an interface is provided between the external device and the system bus 2 or any of the other internal circuit devices.
A case will be described where the entirety of the system formed on an IC such as the IC 3 or a system in which the IC 3 is provided as a part of the relevant system is under development. In such a case, the relevant system will undergo operation analysis, debugging, operation verification, and so on. For this purpose, emulation using an in-circuit emulator (abbreviated ICE, hereinafter) is commonly used.
With reference to FIG. 2, an emulation system using such an ICE will be described. The same reference numerals are given to elements identical to those in the construction of FIG. 1.
An ICE 5 is provided external to an IC 4 comprising the CPU core 1. The ICE 5 comprises an emulator element 6, a pod 7 and a pod cable 8 connecting the emulator element 6 with the pod 7. In the pod 7, an emulation chip 9 is provided which performs operation identical to that in the CPU core 1. The emulation chip 9, through an emulation controller 11, is connected to a bus 10 including bus elements corresponding to all terminals which the CPU core has. The emulation chip controller 11 operates to monitor or alter input signals and output signals associated with the emulation chip 9. The emulator element 6 controls, via the pod cable 8, the entirety of this operation.
In the IC 4, a bus switch 12 is provided between the CPU core 1 and system bus 2. The bus switch 12 connects, in the normal operation state, the CPU core 1 with the system bus 2. The bus switch 12 connects, in the emulation operation state, the CPU bus 10 with the system bus 2, the CPU core 1 being deactivated. Accordingly, in the emulation operation state, the emulation chip 9 is connected to the system bus 2 via the CPU bus 10 and the CPU core 1 is not connected thereto. Thus, the system formed on the IC 4 or the system including the IC 4 is operated under the condition where the emulation chip 9 is substituting for the CPU core 1 as the CPU in the relevant system.
Then, the emulator element 6, via the pod cable 8, performs monitoring, resetting, interruption, and other control of the operation in the emulation chip. Thus, system-operation analysis, debugging and verification are performed on the relevant system, to achieve the initial object as mentioned above.
Thus, in a construction such as described above, the bus connecting the CPU core 1 with the system bus 2, both being integrated in the IC 4, is required to be externally accessible, so as to form the CPU bus 10, from the IC 4 by means of the bus switch 12. As described above, in order to implement the emulation to be performed on the CPU core 1, the emulation chip 9 is required which acts identically to the CPU core 1. Accordingly, it is necessary that the CPU bus 10 comprises all signal lines which are to be connected to all terminals provided on the CPU core 1. Thus, it is necessary that the terminals are provided on the IC 4 comprising the CPU core 1 for the purpose of the emulation, which terminals are not necessary in the non-emulation mode. Thus an increased number of terminal elements need to be provided on the IC 4. The increased number of terminal elements remarkably raises the cost of the IC.
Further, the emulation chip 9 acts instead of the CPU core 1 in the emulation-operation state as described above. The bus switch 12 and the CPU bus 10 lie between the emulation chip 9 and the system bus 2. As a result, a time lag may occur in the signal transfer between the emulation chip 9 and the system bus 2 in comparison to the normal operation mode in which the IC 4 is operated by the CPU core 1. Thus, differences between the two modes may occur. That is, there may be a case where although there occurs no trouble in the normal operation mode in which the CPU core 1 operates the IC 4, incorrect operation occurs due a time lag such as mentioned above in the emulation mode where the emulation chip 9 operates the IC 4.
Further, in a construction such as that comprising a provision such as the bus switch 12, another problem occurs in each development stage of a system such as the IC 4 comprising the CPU core 1. The problem is that, it is necessary to develop, for each CPU architecture, components such as the emulation chip 9 having the same performance as the relevant CPU core 1, and the pod 7 comprising the emulation chip 9. Thus, an increased cost and an lengthy period are required for the development, due to the increased number of components to be developed.